Digital Logics Chapter Wise Important Questions

Digital Logics Chapter Wise Important Questions

Unit 1: Introduction

1. Define analog and digital signals. Explain digital signal with its applications, advantages and disadvantages.
2. What is a digital logic gate? Explain basic logic gates (AND, OR, NOT) with truth tables and logic symbols.
3. Define combinational and sequential logic circuits with examples.
4. What is a clock wave form? Explain its significance in digital circuits.

Unit 2: Number Systems

1. What is a number system? Explain binary, octal, decimal and hexadecimal number systems with examples.
2. Convert the following:
   • (101101)₂ to decimal
   • (45)₁₀ to binary
   • (2594.68)₁₀ to hexadecimal
   • (+64.35) to IEEE 754 double precision floating point binary number
   • (62.75)₁₀ to single precision floating point format
3. Define signed number representation. Explain 1’s complement and 2’s complement with examples.
4. Subtract 23 from 18 using both 1’s and 2’s complement method.
5. Subtract: 1010101.101 − 1000100.001 using both 1’s and 2’s complement.
6. Subtract: 453.35 − 321.17 using both 9’s and 10’s complement.
7. What is floating point number representation? Explain with example.
8. Explain representation of BCD, ASCII, Excess-3, Gray code and Error Detection Codes with examples.
9. Find the Gray code of 1011010.

Unit 3: Combinational Logic Design

Boolean Algebra and Logic Gates

1. What is Boolean algebra? State and prove De Morgan’s theorems with examples.
2. Explain NAND and NOR as universal gates. Realize OR, AND, and NOT gates using only NAND gates and only NOR gates.
3. What are extended/derived gates? Explain EX-OR and EX-NOR gates with truth tables and logic diagrams.
4. Explain canonical forms (SOP and POS). Convert a Boolean expression to standard SOP and POS form.
5. Express the Boolean function F(A,B,C,D) = D(A’+B) + B’D into standard SOP and POS.

K-Map Simplification

6. What is a K-map? Simplify the following using K-map in both SOP and POS forms:
   • F(A,B,C) = Σ(0,2,4,6) and d = Σ(1,3)
   • F(p,q,r,s) = Σ(3,4,7,8,14) with don’t care d(p,q,r,s) = Σ(1,6,9,13)
   • F(A,B,C,D) = Σ(0,1,2,5,7,8,9,10,13,15)
   • F(A,B,C,D) = Π(0,1,3,7,8,12) and Πd(5,10,13,14)
   • F(w,x,y,z) = π(0,2,4,6,8,10,12,14) with don’t care d(w,x,y,z) = π(1,3,9,11)
7. Simplify up to 5-variable Boolean expression using Quine-McCluskey minimization technique (Tabular Method).

Combinational Circuit Design

8. Define combinational circuit. Write the combinational circuit design procedure.
9. Design a half adder and full adder with truth table, logic diagram and Boolean expression.
10. Design a half subtractor and full subtractor with block diagram, truth table, logic diagram and Boolean expression.
11. Explain 4-bit binary parallel adder. Implement full adder using two half adders.
12. Design a full subtractor circuit using decoder and two OR gates.
13. Define multiplexer. Explain 4:1 multiplexer with block diagram, truth table and logic diagram. Implement 8:1 multiplexer using lower-order multiplexers.
14. Design 1:8 DEMUX using 1:4 DEMUX and 1:2 DEMUX.
15. Define decoder. Design BCD to decimal decoder with block diagram, truth table, circuit diagram and mathematical expression.
16. Design binary to octal converter with block diagram, truth table and logic diagram.
17. Define priority encoder. Design 4:2 priority encoder with block diagram, truth table, circuit diagram and mathematical expression.
18. Design 8 to 3 priority encoder in detail.
19. What is a magnitude comparator? Design a 2-bit and 4-bit magnitude comparator.
20. Design a combinational circuit using a ROM that accepts a 3-bit number and generates output equal to the square of the input number.
21. Design a 4-bit magnitude comparator with its working principle.
22. Design a combinational circuit that generates 9’s complement of a 3-input number using 3 gates only.
23. Design a combinational circuit with four inputs representing a decimal digit in BCD and four output lines generating the 2’s complement of the input with circuit diagram, truth table and block diagram.

Programmable Logic

24. Define ROM, PAL and PLA. Differentiate between PAL and PLA.
25. Design a PLA circuit for the following functions:
    • F1(A,B,C) = Σ(3,5,6,7) and F2(A,B,C) = Σ(0,2,4,7)
    • F1(A,B,C) = Σ(2,3,5) and F2(A,B,C) = Σ(0,4,5,7)
26. Realize BCD to Gray code converter using PAL.
27. Define ECL. Explain 3-bit even parity generator and checker.

Unit 4: Counters and Registers

Flip-Flops

1. Define latch. How does a flip-flop differ from a latch?
2. Explain RS, JK, Master-Slave, D and T flip-flops with logic diagram, truth table, characteristic table and excitation table.
3. Explain clocked SR flip-flop with logic diagram, truth table, characteristic table and excitation table.
4. What is race around condition? How does the JK Master-Slave flip-flop eliminate the race around condition? Illustrate with a timing diagram.
5. Explain level triggering and edge triggering with examples.

Counters

6. Differentiate between synchronous and asynchronous (ripple) counters.
7. Design a 3-bit asynchronous up counter with block diagram, count sequence table and timing diagram.
8. Design Mod-7 ripple counter with state diagram, sequence table, logic diagram and timing diagram.
9. Design Mod-10 synchronous counter to count in the sequence 0, 2, 4, 5, 6, 8 using T flip-flop.
10. Design Mod-11 synchronous counter.
11. Design Mod-5 counter with state and timing diagram.
12. Design a 3-bit Gray code synchronous counter.
13. Design Modulus counters (5, 7, 11) with circuit diagrams and state diagrams.
14. Design a Ring counter and explain with state and timing diagram.
15. Explain applications of counters: Digital Watch and Frequency Counter.

Registers

16. What is a register? Explain types of registers (SIPO, SISO, PISO, PIPO) with block diagram and logic diagram.
17. Explain serial in serial out register with working mechanism for data input 11010.
18. Design a 4-bit bidirectional shift register.
19. Explain shift register with parallel load.

Unit 5: Sequential Logic Design

1. Define sequential machine. What are the basic models of sequential machines?
2. Explain the concept of State and State Diagram with examples.
3. What is state reduction? Explain state reduction through partitioning and implementation of synchronous sequential circuits.
4. Explain how flip-flops are used in realizing sequential logic models.
5. Design a counter using the sequential logic design procedure.
6. A sequential circuit with two D flip-flops A and B, one input x and one output z is specified by the following equations:
   • A(t+1) = xy’ + xB, B(t+1) = x’B + xA, z = A + B’ Draw the logic diagram, state table and state diagram.
7. A sequential circuit with two D flip-flops A and B, two inputs x and y, and one output z is specified by:
   • A(t+1) = x’y + xA, B(t+1) = x’B + xA, z = B Draw the logic diagram, derive the state table and state diagram.

📝 Note:This list is for reference purposes only to help you prepare smartly and cover all critical areas of  Digital Logic. Always review your class notes, teacher guidelines, and syllabus coverage.

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